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MIC

    Submitter: William McGrath
    Submitter's Institution: Cornell
    Submission Date: 2014-10-29
    Description: Cornell Virtual Workshop

    Prerequisites: Parallel, batch, computer architecture

    The Xeon Phi coprocessor is a system on a PCIe card designed to provide high levels of floating point performance for highly parallel HPC code. Its architecture is known as Many Integrated Core (MIC). This module describes the MIC architecture behind the Xeon Phi, its performance characteristics, how and when to run code on the coprocessors available within Stampede in order to best take advantage of the resources available.




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