Intel Xeon Phi Native Execution and Optimization

Submitter: William McGrath
Submitter's Institution: TACC
Submission Date: 2016-01-22
Description: TACC

The Innovative Technology component of the XSEDE Stampede supercomputer at TACC provides access to 8 PetaFlops of computing power in the form of the new Intel Xeon Phi Coprocessor, also known as MIC. This workshop is designed to introduce Stampede users to the MIC architecture in a practical manner. Multiple lectures and hands-on exercises will be used to get the user acquainted with the MIC platform and explore the different execution modes as well as parallelization and optimization through example testing and reports. The workshop will be divided in four sections: Introduction to the MIC architecture; native execution and optimization; offload execution; and symmetric execution. In each section the users will spend half the time doing guided hands-on exercises.

• https://www.tacc.utexas.edu/user-services/training/course-materials
  TACC Training Materials


• https://portal.tacc.utexas.edu/-/optimize-your-code-for-the-intel-xeon-p-1
  TACC Training Materials

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